VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 13: CPU: Synthesis Description
Overview
In this chapter, we further refine the CPU description and examine the RTL (Register Transfer Level) description of the CPU. The CPU is described by a number of lower-level components that are instantiated to form the CPU design. At the top of the CPU design is an architecture that instantiates all of the lower-level components to form the CPU. The CPU block diagram is shown in Figure 13-1.
Figure 13-1: CPU Block Diagram.
Following is an implementation of this block diagram, shown by file cpu.vhd:
<b class="bold">library IEEE;</b><b class="bold">use IEEE.std_logic_1164.all;</b><b class="bold">use work.cpu_lib.all;</b><b class="bold">entity cpu is</b><b class="bold"> port(clock, reset, ready : in std_logic;</b><b class="bold"> addr : out bit16;</b><b class="bold"> rw, vma : out std_logic;</b><b class="bold"> data : inout bit16);</b><b class="bold">end cpu;</b><b class="bold">architecture rtl of cpu is</b><b class="bold"> component regarray</b><b class="bold"> port( data : in bit16;</b><b class="bold"> sel : in t_reg;</b><b class="bold"> en : in std_logic;</b><b class="bold"> clk : in std_logic;</b><b class="bold"> q : out bit16);</b><b class="bold"> end component;</b>
<b class="bold"> component reg</b><b class="bold"> port( a : in bit16;</b><b class="bold"> clk : in std_logic;</b><b class="bold"> q : out bit16);</b><b class="bold"> end component;</b><b class="bold"> component trireg</b><b class="bold"> port( a :...
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