VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 10: VHDL Synthesis
In this chapter, we focus on how to write VHDL that can be read by synthesis tools. We start out with some simple combinational logic examples, move on to some sequential models, and end the chapter with a state machine description.
All of the examples are synthesized with the Exemplar Logic Leonardo synthesis environment. The technology library used is an example library from Exemplar Logic. All of the output data should be treated as purely sample outputs and not representative of how well the Exemplar Logic tools work with real design data and real constraints.
Simple Gate Concurrent Assignment
The first example is a simple description for a 3-input OR gate:
<b class="bold">LIBRARY IEEE;</b><b class="bold">USE IEEE.std_logic_1164.ALL;</b><b class="bold">ENTITY or3 IS</b><b class="bold"> PORT (a, b, c : IN std_logic;</b><b class="bold"> d : OUT std_logic);</b><b class="bold">END or3;</b><b class="bold">ARCHITECTURE synth OF or3 IS</b><b class="bold">BEGIN</b><b class="bold"> d <= a OR b OR c;</b><b class="bold">END synth;</b>
This model uses a simple concurrent assignment statement to describe the functionality of the OR gate. The model specifies the functionality required for this entity, but not the implementation. The synthesis tool can choose to implement this functionality in a number of ways, depending on the cells available in the technology library and the constraints on the model. For instance, the most obvious implementation is shown in Figure 10-1.
Figure 10-1: Model Implementation.
This implementation uses a 3-input OR gate to implement the functionality specified in the concurrent signal...
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