Overview

After the CPU has been functionally verified, the design can be implemented in actual hardware. This chapter describes the synthesis process and synthesis results of the CPU RTL description. The VHDL design description is optimized and mapped to a programmable logic device. As opposed to an ASIC device, these devices can be programmed by designers at their desks, and most can be reprogrammed to fix errors later.

A synthesis tool is used to read in the VHDL description and map the description to the target programmable logic device. The synthesis tool reads all the VHDL source files, links them together (elaborate), optimizes the design, and then maps the optimized description to the target technology. The synthesis tool used is the Leonardo Spectrum synthesis tool from Exemplar Logic. This is a popular synthesis tool in the FPGA ( Field Programmable Gate Array) market and produces very good results quickly.

Figure 15-1: Leonardo Spectrum User Interface.

The first step in the synthesis process is to read all the files of the design into the synthesis tool. This can be accomplished either by using the synthesis tool GUI ( Graphical User Interface) or by issuing command language commands. First time or casual users will probably use the GUI because no command language syntax knowledge is required, and all operations can be accomplished through menu clicks. Everyday users of the tool quickly learn the command language of the synthesis tool, create scripts that build up the design, and run those...