VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 3: Sequential Processing
In Chapter 2, we examined behavioral modeling using concurrent statements. We discussed concurrent signal assignment statements, as well as block statements and component instantiation. In this chapter, we focus on sequential statements. Sequential statements are statements that execute serially one after the other. Most programming languages, such as C and C++, support this type of behavior. In fact, VHDL has borrowed the syntax for its sequential statements from ADA.
Process Statement
In an architecture for an entity, all statements are concurrent. So where do sequential statements exist in VHDL? There is a statement called the process statement that contains only sequential statements. The process statement is itself a concurrent statement. A process statement can exist in an architecture and define regions in the architecture where all statements are sequential.
A process statement has a declaration section and a statement part. In the declaration section, types, variables, constants, subprograms, and so on can be declared. The statement part contains only sequential statements. Sequential statements consist of CASE statements, IF THEN ELSE statements, LOOP statements, and so on. We examine these statements later in this chapter. First, let s look at how a process statement is structured.
Sensitivity List
The process statement can have an explicit sensitivity list. This list defines the signals that cause the statements inside the process statement to execute whenever one or more elements of the list change value. The sensitivity list is a list of the signals that will cause the process to execute.
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