VHDL: Programming By Example, Fourth Edition
No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast or as painlessly as this classic tutorial.
TABLE OF CONTENTS VHDL: Programming By Example, Fourth Edition
Chapter 16: Place and Route
This chapter discusses the process of implementing the synthesis netlist of the CPU design into a target FPGA device. The place and route tools read the netlist, extract the components and nets from the netlist, place the components on the target device, and interconnect the components using the specified interconnections. After the place and route process is complete, the designer has an implementation of the design in the target technology. The implementation still needs to be verified for logical and timing correctness.
Figure 16-1: Place and Route Process.
Place and Route Process
The place and route process places each macro from the synthesis netlist into an available location on the target silicon and connects the macros using routing resources available on the target silicon. The place and route process is shown in Figure 16-1.
The synthesis netlist is input to the placement process. The placement process analyzes all of the macros used in the design and their connectivity to try to determine an optimal placement for the macros. The placement algorithms take into account a number of technology-specific factors of the target technology to determine whether a particular placement is good or not. After a trial placement and signal route is attempted, the design is analyzed with respect to timing constraints. If the timing constraints are not met, the place and route software continues to try different placements and signal routing to try to meet the constraints.
Typical target devices have areas of the chip where logical functions are...
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