TABLE OF CONTENTS The supported instructions are listed in Tables 4.2 4.9. The complete details of each instruction are available in the ARM v7-M Architecture Application Level Reference Manual (Ref 2). There is also a summary of the supported instruction sets in Appendix A.
| Instruction | Function |
|---|---|
| ADC | Add with carry |
| ADD | Add |
| AND | Logical AND |
| ASR | Arithmetic shift right |
| BIC | Bit clear (Logical AND one value with the logic inversion of another value) |
| CMN | Compare negative (compare one data with two's complement of another data and update flags) |
| CMP | Compare (compare two data and update flags) |
| CPY | Copy (available from architecture v6; move a value from one high or low register to another high or low register) |
| EOR | Exclusive OR |
| LSL | Logical shift left |
| LSR | Logical shift right |
| MOV | Move (can be used for register-to-register transfers or loading immediate data) |
| MUL | Multiply |
| MVN | Move NOT (obtain logical inverted value) |
| NEG | Negate (obtain two's complement value) |
| ORR | Logical OR |
| ROR | Rotate right |
| SBC | Subtract with carry |
| SUB | Subtract |
| TST | Test (use as logical AND; Z flag is updated but AND result is not stored) |
| REV | Reverse the byte order in a 32-bit register (available from architecture v6) |
| REVH | Reverse the byte order in each 16-bit half word of a 32-bit register (available from architecture v6) |
| REVSH | Reverse the byte order in the lower 16-bit half word of a 32-bit register and sign extends the result to 32 bits, (available from architecture v6) |
| SXTB | Signed extend byte... |
