TABLE OF CONTENTS | Exception Type | Name | Priority (Level Address) | Enable |
|---|---|---|---|
| 1 | Reset | -3 | Always |
| 2 | NMI | -2 | Always |
| 3 | Hard fault | -1 | Always |
| 4 | MemManage | Programmable (0xE000ED18) | NVIC SHCSR (0xE000ED24) bit[16] |
| 5 | BusFault | Programmable (0xE000ED19) | NVIC SHCSR (0xE000ED24) bit[17] |
| 6 | Usage fault | Programmable (0xE000ED1A) | NVIC SHCSR (0xE000ED24) bit[18] |
| 7 10 | - | - | - |
| 11 | SVC | Programmable (0xE000ED1F) | Always |
| 12 | Debug monitor | Programmable (0xE000ED20) | NVIC DEMCR (0xE000EDFC) bit[16] |
| 13 | - | - | - |
| 14 | PendSV | Programmable (0xE000ED22) | Always |
| 15 | SysTick | Programmable (0xE000ED23) | SYSTICK CTRLSTAT (0xE000E010) bit[1] |
| 16 255 | IRQ | Programmable (0xE000E400) | NVICSETEN (0xE000E100) |
| Address | Data | Push Order |
|---|---|---|
| Old SP (N) -> | (Previously pushed data) | - |
| (N-4) | PSR | 2 |
| (N-8) | PC | 1 |
| (Nv12) | LR | 8 |
| (N-16) | R12 | 7 |
| (N-20) | R3 | 6 |
| (N-24) | R2 | 5 |
| (N-28) | R1 | 4 |
| New SP (N-32) -> | R0 | 3 |
| Note: If double word stack alignment feature is used and the SP was not double word aligned when the exception occured, the stack frame top might begin at ((OLD_SP-4) AND OXFFFFFFF8), and the rest of the tabe moves one word down. |
