TABLE OF CONTENTS Several useful Thumb-2 instructions from the architecture v7 and v6 are introduced here.
These two instructions provide access to the special registers in the Cortex-M3. Here is the syntax of these instructions:
MRS, ; Move from Special Register MSR , ; Write to Special Register
where
| Symbol | Descrip tion |
|---|---|
| IPSR | Interrupt status register |
| EPSR | Execution status register (read as zero) |
| APSR [a] | Flags from previous operation |
| IEPSR | A composite of IPSR and EPSR |
| IAPSR | A composite of IPSR and APSR |
| EAPSR | A composite of EPSR and APSR |
| PSR | A composite of APSR, EPSR and IPSR |
| MSP | Main stack pointer |
| PSP | Process stack pointer |
| PRIMASK | Normal exception mask register |
| BASEPRI | Normal exception priority mask register |
| BASEPRI_MAX | Same as normal exception priority mask register, with conditional write (new priority level must be higher than the old level) |
| FAULTMASK | Fault exception mask register (also disables normal interrupts) |
| CONTROL | Control register |
| [a]In older ARM Cortex-M3 documents, the APSR was called FPSR. If you are using older software development tools that were developed during the early stages of Cortex-M3 development, you might need to use the register name FPSR in your assembly code. |
For example, the following code can be used to set up the Process Stack Pointer:
