TABLE OF CONTENTS The SYSTICK register in the NVIC was covered briefly in Chapter 8. As we saw, the SYSTICK timer is a 24-bit down counter. Once it reaches zero, the counter loads the reload value from the RELOAD register. It does not stop until the enable bit in the SYSTICK Control and Status register is cleared.
The Cortex-M3 processor allows two different clock sources for the SYSTICK counter. The first one is the core free-running clock (not from the system clock HCLK, so it does not stop when the system clock is stopped). The second one is an external reference clock. This clock signal must be at least two times slower than the free-running clock because this signal is sampled by the free-running clock. Because a chip designer might decide to omit this external reference clock in the design, it might not be available. To determine whether the external clock source is available, you should check bit[31] of the SYSTICK Calibration register. The chip designer should connect this pin to an appropriate value base on the design.
When the SYSTICK timer changes from 1 to 0, it will set the COUNTFLAG bit in the SYSTICK Control and Status register. The COUNTFLAG can be cleared by one of the following:
Read of the SYSTICK Control and Status register by the processor
Clear of the SYSTICK counter value by writing any value to the SYSTICK Current Value register
The SYSTICK counter can be used...
