TABLE OF CONTENTS This material is reproduced from the Cortex-M3 Technical Reference Manual with permission from ARM Limited. Instructions marked with a plus sign (+) indicate that the flag (APSR) gets updated.
| Assembler | Operation |
|---|---|
|
ADC | Add register value and C flag to register value:
Rd = Rd + Rm + C |
|
ADD | Add immediate 3-bit value to register:
Rd = Rn + immed_3 |
|
ADD | Add immediate 8-bit value to register:
Rd = Rd + immed_8 |
|
ADD | Add low register value to low register value:
Rd = Rn + Rm |
|
ADD | Add high register value to low or high register value |
|
ADD | Add 4 (immediate 8-bit value) + (word aligned PC value) to register:
Rd = PC + 4*immed_8 |
|
ADD | Add 4 (immediate 8-bit value) + (word aligned SP value) to register:
Rd = SP + 4* immed_8 |
|
ADD SP, # | Add 4 (immediate 7-bit value) to SP:
SP = SP + 4* immed_7 |
|
AND | Bitwise AND register:
Rd = Rd AND Rm |
|
ASR | Arithmetic shift right by immediate number:
Rd = Rm >> immed_5 |
|
ASR | Arithmetic shift right by number in register:
Rd = Rm >> Rs |
|
B | Branch conditional:
if |
|
B | Branch unconditional:
PC = (PC+4) + (SignExtend (target_address_11) *2) |
|
BIC |
