TABLE OF CONTENTS | Bits | Name | Type | Reset Value | Description |
|---|---|---|---|---|
| 4:0 | INTLINESNUM | R | - | Number of interrupt inputs in step of 32: 0 = 1 to 32 1 = 33 to 64
|
| Bits | Name | Type | Reset Value | Descriptions |
|---|---|---|---|---|
| 16 | COUNTFLAG | R | 0 | Read as 1 if counter reach 0 since last time this register is read. Clear to 0 automatically when read or when current counter value is cleared. |
| 2 | CLKSOURCE | R/W | 0 | 0 = external reference clock (STCLK) 1 = use core clock |
| 1 | TICKINT | R/W | 0 | 1 = Enable SYSTICK interrupt generation when SYSTICK timer reaches 0 0 = Do not generate interrupt |
| 0 | ENABLE | R/W | 0 | SYSTICK timer enable |
| Bits | Name | Type | Reset Value | Descriptions |
|---|---|---|---|---|
| 23:0 | RELOAD | R/W | 0 | Reload value when timer reaches 0 |
| Bits | Name | Type | Reset Value | Descriptions |
|---|---|---|---|---|
| 23:0 | CURRENT | R/Wc | 0 | Read to return current value of the timer Write to clear counter to 0; clearing of current value should also clear COUNTFLAG in SYSTICK Control and Status register |
| Bits | Name | Type | Reset Value | Description |
|---|---|---|---|---|
| 31 | NOREF | R | - | 1 = No external reference clock (STCLK not available) 0 = External reference clock available |
| 30 | SKEW | R | - | 1 = calibration value is not exactly 10 ms 0 = calibration value is accurate |
| 23:0 | TENMS | R/W | 0 | Calibration value for... |
