TABLE OF CONTENTS One of the challenges of using the Cortex-M3 is to locate problems when the program goes wrong. The Cortex-M3 processor provides a number of fault status registers to assist in troubleshooting (see Table E.1).
| Address | Register | Full Name | Size |
|---|---|---|---|
| 0xE000ED28 | MMSR | MemManage Fault Status register | Byte |
| 0xE000ED29 | BFSR | Bus Fault Status register | Byte |
| 0xE000ED2A | UFSR | Usage Fault Status register | Half word |
| 0xE000ED2C | HFSR | Hard Fault Status register | Word |
| 0xE000EDS0 | DFSR | Debug Fault Status register | Word |
| 0xE000ED3C | AFSR | Auxiliary Fault Status register | Word |
The MMSR, BFSR, and UFSR registers can be accessed in one go using a word transfer instruction. In this situation the combined fault status register is called the Configurable Fault Status Register (CFSR).
Another important piece of information is the stacked Program Counter (PC). This is located in memory address [SP + 0x24]. Since there are two stack pointers in the Cortex-M3, the fault handler might need to determine which stack pointer was used before obtaining the stacked PC.
In addition, for bus faults and memory management faults, you might also able to determine the address that caused the fault. This is done by accessing the MemManage (Memory Management) Fault Address Register (MMAR) and the Bus Fault Address Register (BFAR). The contents of these two registers are only valid when the MMAVALID bit (in MMSR) or BFARVALID bit (in BFSR) is set. The MMAR and BFAR are physically the same register, so only one of them can be valid at...
