TABLE OF CONTENTS When an exception takes place, a number of things happen:
Stacking (pushing eight registers' contents to stack)
Vector fetch (reading the exception handler starting address from the vector table)
Update of the stack pointer, link register, and program counter
When an exception takes place, the registers PC, PSR, R0 R3, R12, and LR are pushed to the stack. If the code that is running uses the PSP, the process stack will be used; if the code that is running uses the MSP, the main stack will be used. Afterward, the main stack will always be used during the handler, so all nested interrupts will use the main stack.
The order of stacking is shown in Figure 9.1 (assuming that the SP value is N before the exception). Due to the pipeline nature of the AHB interface, the address and data are offset by one pipeline state.
The values of PC and PSR are stacked first so that instruction fetch can be started early (which requires modification of PC) and the IPSR can be updated early. After stacking, SP will be updated to N-32 (0 20), and the stacked data arrangement in the stack memory will look like Table 9.1.
| Address | Data | Push Order |
|---|---|---|
| Old SP (N)-> | (Previously pushed data) | - |
| (N-4) | PSR | 2 |
| (N-8) | PC | 1 |
| (N-12) | LR | 8 |
| (N-16) | R12 | 7 |
| (N-20) | R3 | 6 |
| (N-24) | R2 | 5 |
| (N-28) | R1 | 4 |
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