TABLE OF CONTENTS The Cortex-M3 provides a feature-packed exception architecture that supports a number of system exceptions and external interrupts. Exceptions are numbered 1 to 15 for system exceptions and 16 and above for external interrupt inputs. Most of the exceptions have programmable priority, and a few have fixed priority.
Cortex-M3 chips can have different numbers of external interrupt inputs (from 1 to 240) and different numbers of priority levels. This is because chip designers can configure the Cortex-M3 design source code for different needs.
Exception types 1 to 15 are system exceptions (there is no exception type 0), as outlined in Table 7.1. Exceptions of type 16 or above are external interrupt inputs (see Table 7.2).
| Exception Number | Exception Type | Priority | Description |
|---|---|---|---|
| 1 | Reset | -3 (Highest) | Reset |
| 2 | NMI | -2 | Nonmaskable interrupt (external NMI input) |
| 3 | Hard Fault | -1 | All fault conditions, if the corresponding fault handler is not enabled |
| 4 | MemManage Fault | Programmable | Memory management fault; MPU violation or access to illegal locations |
| 5 | Bus Fault | Programmable | Bus error; occurs when AHB interface receives an error response from a bus slave (also called prefetch abort if it is an instruction fetch or data abort if it is a data access) |
| 6 | Usage Fault | Programmable | Exceptions due to program error or trying to access coprocessor (the Cortex-M3 does not support a coprocessor) |
| 7 10 | Reserved | NA | - |
| 11 | SVCall | Programmable | System Service call |
| 12 | Debug Monitor | Programmable | Debug monitor (breakpoints, watchpoints, or external... |
