VLIW Microprocessor Hardware Design: For ASIC and FPGA

Chapter 3: RTL Coding, Testbenching, and Simulation

Overview

Section 2.2 in Chapter 2 shows the architecture and Section 2.3 shows the microarchitecture of the VLIW microprocessor. Once the microarchitecture has been defined with the intermodule signals, the next step is to write the RTL code and testbenches to verify the code.

The RTL code is written based on the functionality of the design blocks or modules that are defined in the microarchitecture. For example, the fetch module will have the RTL code written for the functionality of fetching the VLIW instruction and data from external memory module to the decode module.

Note

RTL is register transfer level. RTL code refers to code that is written to reflect the functionality of a design. RTL code can be synthesized to logic gates using logic synthesis tools.

Note

There are three types of verilog code: structural, RTL, and behavioral. Structural verilog code describes the netlist of a design. An example of structural verilog is as follows:

AND and_inst_0 (.O(abc), .I1(def), .I2(ghi));

OR or_inst_3 (.O(xyz), .I1(kjl), .I2(mbp), .I3(hyf));

RTL code describes the functionality of a design and is synthesizable. Behavioral code describes the behavior of a design as a black box. It does not have details on how the functionality of a design is achieved, but rather a behavioral description of the design. Behavioral codes are normally used for verification and not for synthesis.

When writing the RTL code, it is important to follow a certain set of coding rules in order to have an efficient code that...