TABLE OF CONTENTS Static timing analysis is the process of timing verification that verifies a design for setup time violation and hold time violation.
Setup time violation occurs when a path takes longer than the required time. If a path has setup time violation, that path is too slow compared to the required timing. To fix a setup time violation, the path must be optimized for faster timing. Figure 3.33 shows a path that has a setup time violation.
Referring to Figure 3.33, the rising clock edge flip-flop has a setup time requirement of 1 ns. In order for the flip-flop to capture the data at input D during the rising edge of clock, the data at input D must be valid before the setup time requirement of the flip-flop. In this case, the signal at netB must be valid at least 1 ns before the rising edge of clock. Figure 3.34 shows a timing diagram of signal netB with a setup time requirement of the flip-flop.
Referring to Figure 3.34, the signal netB is valid at time t x before the rising edge of clock. Signal netB meets the setup time requirement if t x > t setup. Based on this requirement, the circuit shown in Figure 3.33 has a setup time violation because...
