VLIW Microprocessor Hardware Design: For ASIC and FPGA

3.9: RC Extraction

3.9 RC Extraction

As described in Section 3.4, during pre-layout synthesis the interconnect delays are estimated based on statistical wireload model. Therefore, the timing information obtained is inaccurate and estimated. When layout is completed with DRC and LVS clean, the accurate delay for each interconnect is extracted and calculated in RC extraction. The extracted information can be in the form of sdf (standard delay format), dspf, or spef format. This extracted delay is used for post-layout logic verification and post-layout performance verification.