VLIW Microprocessor Hardware Design: For ASIC and FPGA

Appendix A: Testbenches and Simulation Results

Appendix A shows several of the testbenches used for verifying the VLIW microprocessor. A complete verification plan consists of many tests to fully verify each functionality and feature of the VLIW microprocessor. Example A.1 shows the verilog code for a testbench verifying the functionality of operation barrel shift left, subtract, multiply, and read.

Example A.1: Testbenches Verifying Barrel Shift Left, Subtract, Multiply, and Read
     module vliw_top_tb();     reg clock, reset;     reg [191:0] data;     reg [63:0] word;     wire [63:0] readdatapipe1, readdatapipe2, readdatapipe3;     wire jump;     parameter halfperiod = 5;     parameter twocycle = 20;     parameter delay = 100;     //  include the file that declares the parameter declaration for     //  register     // names and also instruction operations     'include "/project/VLIW/64bit/simulation/regname.v"     //  clock generation     initial     begin        clock = 0;        forever #halfperiod clock = ~clock;     end     // pump in stimulus for vliw processor     initial     begin         // do a reset   ...