VLIW Microprocessor Hardware Design: For ASIC and FPGA

3.1: Coding Rules

3.1 Coding Rules

The coding rules described in this chapter are a set of generic coding rules that can be used as a guideline to ensure good coding style as well as to obtain good verilog code to ensure optimal synthesis. Not having a good set of coding rules can result in badly coded RTL, which can cause a synthesis tool to synthesize redundant logic to a design. This will result in a greater number of logic gates. Alternately, the synthesis tool may also synthesize garbage logic, causing a mismatch between the RTL simulation and the synthesized logic circuit.

  1. Use comments in RTL code. Many inexperienced designers often neglect putting comments into RTL code. This may cause difficulty when the RTL code is reused or reanalyzed at a later stage, because the original designer may have forgotten the reasons for the RTL code. Adding comments to a RTL code makes it readable and easier to understand. It is a good coding practice to always use comments when writing code.

  2. Module name matching filename. Section 2.3 explained the advantages of using a naming convention for intermodule signals. Apart from the signals having a naming convention, it is good practice to ensure that the filename of the RTL code matches the module name of the code. Each filename should only have one RTL module. Following this rule makes the fullchip easily readable, especially when the fullchip is a large ASIC or SOC design that consists of many files.

  3. Output of...