TABLE OF CONTENTS After verifying the simulation results of the design, the next step is to synthesize the design. Synthesis is the process of converting and mapping the RTL verilog code into logic gates based on a standard cell library.
The process of synthesis requires three separate inputs:
standard cell library
design constraints
RTL design code
Synthesis can be categorized into pre-layout synthesis and post-layout synthesis. Pre-layout synthesis is synthesis on the RTL code using estimation on the interconnects between gates. Pre-layout synthesis uses wireload models which are statistical models of estimation on interconnects. Post-layout synthesis is an incremental synthesis process that is performed after layout. The interconnects between gates are accurately extracted after layout and back annotated for post-layout synthesis.
A standard cell library is a library that consists of many different types of logic gates (and, or, not, nand, nor, xor, flip-flop, latch, and-nor, ornand, and many others) with different types of sizing. A standard cell library normally consists of the following:
basic logic gates
| i. | and_a, and_b, and_c |
| ii. | or_a, or_b, or_c |
| iii. | nand_a, nand_b, nand_c |
| iv. | nor_a, nor_b, nor_c |
| v. | not_a, not_b, not_c, not_d, not_e, ... not_j |
| vi. | xor_a, xor_b, xor_c |
complex logic gates
| vii. | and_nor_a, and_nor_b, and_nor_c (refer to Figure 3.21) |
| viii. | or_nand_a, or_nand_b, or_nand_c (refer to Figure 3.22) |
| ix. | or_or_nand_a, or_or_nand_b, or_or_nand_c (Refer to Figure 3.23) |
| x. | and_and_nor_a, and_and_nor_b, and_and_nor_c (refer to Figure 3.24) |
Figure 3.21: Diagram showing different types of and_nor gates.
Figure 3.22: Diagram showing different types of...
