VLIW Microprocessor Hardware Design: For ASIC and FPGA

Appendix B: Synthesis Results, Gate Level Netlist

Table B.1 shows the ASIC synthesized results in terms of performance and area of the VLIW microprocessor implemented on a 0.35 micron technology.

Table B.1: Synthesis Results of VLIW Microprocessor Implemented on 0.35 Micron Technology

Module

Performance (MHz)

Transistor Count

Fetch

450

9788

Decode

600

9068

Execute

90

156374

Register file

300

147414

Writeback

900

16544

In Table B.1, the VLIW microprocessor is limited in performance by the execute unit because it is the slowest unit due to the large ALU required to perform the VLIW microprocessor s computation. The performance for the VLIW microprocessor therefore is limited to 270 MIPS (maximum performance of 3 operations per clock cycle but varies depending on application).

Example B.1 shows a portion of the gate level netlist generated from synthesis utilizing a 0.35-micron standard cell library.

Example B.1: Verilog Gate Netlist of VLIW Microprocessor
    //    // Verilog description for cell vliw_top,    // 07/20/05 10:41:53    //

  //  LeonardoSpectrum  Level 3,  2004a.30  //  module vliw_top ( clock, reset, word, data, readdatapipe1, readdatapipe2,readdatapipe3,  readdatavalid, jump ) ;      input clock ;      input reset ;      input [63:0]word ;      input [191:0]data ;      output [63:0]readdatapipe1 ;      output [63:0]readdatapipe2 ;      output [63:0]readdatapipe3 ; ...