3.3: Testbenches and Simulation
3.3 Testbenches and Simulation
When the RTL code of a design is completed, the next step would be to create testbenches to simulate the design. Testbenches can be in many different forms. Some design engineers use verilog, VHDL, C, systemC, systemVerilog or a mixture of them. Whatever the language used for writing testbench, the end result is the same: creation of testbenches used for simulating the design.
Testbenches is a wrap-around of a design, which allows the testbench to pump in stimulus into the design under test, and monitoring the output of the design. If the output waveforms of the design are not as expected, a bug has occurred. The bug could be in the design or in the testbench.
When a bug is found, the designer must debug the waveforms and decide if it is from the design or the testbench. Either way, the bug must be fixed and simulation is performed again. Only when the output waveform of the design is as expected can the designer proceed to the next phase of the design flow (synthesis).
Figure 3.17 shows how a testbench can wrap around a design for simulation.
Figure 3.17: Diagram showing a testbench wrapping around a design under test.
Figure 3.18 shows the flow used for simulation of RTL design using testbenches. The testbench and RTL code of the design are simulated using a verilog simulator. There are many verilog simulators available in the market, for example, Modelsim from Mentor Graphics, VCS from Synopsys, NC Verilog...