TABLE OF CONTENTS Upon completion of pre-layout synthesis as mentioned in Section 3.4, the synthesized gate level netlist is passed to layout. In the layout process, the synthesized circuit is implemented using physical fabrication layers. During this process, the layout designer uses different layers (poly, metal, n+, p+, and others) to form transistors, logic gates, resistors, and capacitors. Figure 3.37 shows an example of layout of an inverter (layout design in Mentor Graphics IC Station).
There are three methods of performing layout:
manual/custom layout
semi-custom/auto layout
auto place and route
Each of the methods requires a different amount of engineering resource and each has its own set of layout issues that must be addressed carefully.
Manual/custom layout as the name implies is based on layout performed manually by a layout designer. Manual/custom layout is tedious and time consuming as all transistors, logic gates, capacitors, and resistors are drawn manually. The size of each transistor (W/L) is manually measured and drawn in layout. Examples of some manual layout tools are Mentor Graphics IC Station and Cadence s Virtuoso.
Although manual/custom layout is tedious and time consuming, it creates layouts that are smaller and therefore creates silicon dies that are compact and lower in cost. Due to its smaller die size, custom layout also provides for better design performance. A small die translates to shorter interconnects, which in turn translates to smaller interconnect...
