3.10: Post-layout Logic Verification
3.10 Post-layout Logic Verification
This process is referred to as gate level simulation. It involves resimulation of the design using the gate level netlist, extracted gate level delay, and interconnect delay from RC extraction. This step allows for an accurate simulation of the gate level functionality with accurate delay of each gate and net. Any functionality failure during this process may be caused by timing issues such as race conditions or glitches. Any failures caught must be fixed using synthesis tweaks for incremental synthesis, layout tweaks for incremental layout improvements, or in some extreme conditions rewriting the RTL code. Figure 3.38 shows the flow for post-layout logic verification.
Figure 3.38: Diagram showing design flow for post-layout logic verification.
Post-layout logic verification uses large amounts of computation power and requires long simulation time due to the large amount of delay information for gate and interconnect obtained from RC extraction.