TABLE OF CONTENTS When layout is completed, the layout must be verified for a set of design rules specified by the fab. For example, if the VLIW microprocessor is to be fab by Silterra s 0.35 micron process, the layout of the VLIW microprocessor must be verified by a set of design rules specified by Silterra for its 0.35 micron process technology. The design rules specify rules of fabrication that must be met prior to fabrication. Some examples of design rules are as follows:
minimum active area width
minimum active area spacing
minimum N channel body implant spacing
minimum poly width
minimum poly spacing
minimum N+ implant spacing
minimum contact spacing
minimum contact to gate spacing
minimum metal width
minimum metal spacing
During the design rule check (DRC) process, a check for any violations to the fab s specified rules is performed. If any violations occur, the layout designer must fix them in layout. DRC is performed again to verify the fixes. This is repeated until the design does not have any DRC violations.
Once DRC is verified clean, the layout designer will perform layout versus schematic (LVS). In LVS, layout is verified to match the schematic (the schematic can be a custom designed schematic or a synthesized schematic). If any violations occur (layout does not match schematic), the layout designer will have to fix these violations. When DRC and LVS are both verified clean, the design proceeds to RC extraction.
