VLIW Microprocessor Hardware Design: For ASIC and FPGA

3.2: RTL Coding

3.2 RTL Coding

Section 3.1 shows a list of coding rules as a guideline when writing RTL code. These rules must be followed in order to obtain good RTL code that can translate to optimal synthesis results.

Referring to the architectural diagram of Figure 2.3 and microarchitectural diagram of Figure 2.6, the VLIW microprocessor consists of four stages (named fetch, decode, execute and writeback). For ease of understanding, each operation is numbered and categorized as pipe1, pipe2, and pipe3 with pipe1 operating operation 1, pipe2 operating operation 2, and pipe3 operating operation 3. All three operations within the VLIW instruction word have access to a sixteen 64-bit register file.

The RTL code for the VLIW microprocessor can be split into five separate modules: fetch, decode, execute, writeback , and register file (refer to Figure 2.6).

3.2.1 Module fetch RTL Code

The fetch module s functionality is to fetch VLIW instruction and data from an external instruction/data cache as shown in Figure 2.5. The fetched information is passed to the decode module to allow the instruction to be decoded. It is also passed to the register file module to allow the execute module to retrieve data from its register file for those operations that access internal registers.

Table 3.6 shows the interface signals for the fetch module and its interface signal functionality. Figure 3.7 shows the interface signal diagram of the fetch module.