Circuit Design: Know It All

Chapter 17: Dealing with High-Speed Logic

Walt Kester

Overview

Much has been written about terminating printed circuit board traces in their characteristic impedance to avoid reflections. A good rule of thumb to determine when this is necessary is: Terminate the line in its characteristic impedance when the one-way propagation delay of the PCB track is equal to or greater than one-half the applied signal rise/fall time (whichever edge is faster). A conservative approach is to use a 2-inch (PCB track length)/nanosecond (rise/fall time) criterion. For example, PCB tracks for high speed logic with rise/fall time of 1 ns should be terminated in their characteristic impedance if the track length is equal to or greater than 2 inches (including any meanders). Figure 17.1 shows the typical rise/fall times of several logic families including the SHARC DSPs operating on 3.3V supplies. As would be expected, the rise/fall times are a function of load capacitance.

  • GaAs: 0.1 ns,

  • ECL: 0.75 ns,

  • ADI SHARC DSPs: 0.5 ns to 1 ns (operating on 3.3V supply).


Figure 17.1: Typical DSP output rise times and fall times

This same 2-inch/nanosecond rule of thumb should be used with analog circuits in determining the need for transmission line techniques. For instance, if an amplifier must output a maximum frequency of f max, then the equivalent rise time, t r, can be calculated using the equation t r = 0.35/f max. The maximum PCB track length is then calculated by multiplying the rise time by 2 inch/nanosecond. For example, a maximum...

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