Writing Testbenches using SystemVerilog

In this chapter, I describe the verification plan as a specification of the functional verification process and of the testbench infrastructure that will be necessary to support it. It is used to define what is first-time success, how a design is verified and which testbenches are written.
The design project that sits before you will propel your company to new levels of market share and profitability. A few system architects have designed and specified a system that should meet performance and cost goals. Several design leaders, using the system specification, have been working on writing detailed functional specification documents for each of the ASICs and FPGAs that are required to build this new product. Teams of hot-shot hardware designers are being assembled to implement each ASIC or FPGA. Using the detailed specification documents for each device, they are coming up with a detailed implementation schedule. So far, it appears that the project will meet its production deadline.
You are in charge of the verification for this design. Not only must this product be on time, but also it must be functionally correct. The commercial success and profitability of the product depends on it. You have been asked by the project manager to produce a detailed schedule for the verification and define your staffing requirements. How can you determine either?
| Note | Traditionally, verification is an ad-hoc process. |
In a traditional verification process, your decision would be simple. In fact, your own position would not...