This section describes techniques to structure and encapsulate high-level code for maximum maintainability. Encapsulation can be used to hide implementation details and package reusable code elements.

Structuring code is the process of allocating portions of the functionality to different modules or entities. These modules or entities are then connected together to provide the complete functionality of the design. There are many guidelines covering the structure of synthesizable code. That structure has a direct impact on the ease of meeting timing requirements. The structure of a synthesizable model is dictated by the limitations of the synthesis tools, often with little regard to the functionality.

A testbench implemented using high-level SystemVerilog code does not face similar restrictions. You are free to structure your code any way you like. For maintainability reasons, high-level code is structured according to functionality or need. If a function is particularly complex, it is easier to break it up into smaller, easier to understand subfunctions. Or, if a function is required more than once, it is easier to code and verify it separately. Then you can use it as many times as necessary with little additional efforts. System-Verilog code can be structured using task, function, class, module, program, interface, package or inheritance.