In my many years of consulting in design verification, I have yet to see a single testbench that simulates with identical results on different simulators. Half the time, these same testbenches can produce different results by using different command-line options or use a different version of the same simulator! Yet, all simulators are fully compliant with the IEEE standard. Most of the time, the differences are due to race conditions (see "Race Conditions" on page 176). Sometimes, the differences are due to different interpretations of the standard: Many implementation details were left unspecified or existing discrepancies between simulators were also declared "unspecified". Simulator vendors are thus free to implement these unspecified portions of the standard any way they want, yielding different simulation results.

The primary cause of the simulation differences are the authors. SystemVerilog appears easy to learn because it produces the expected response rather quickly. Making sure that the results are reproducible under different conditions is another matter. Learning the idiosyncrasies of the language are what takes time and differentiates an experienced modeler from a new one. It is possible to write testbenches that will simulate with identical results on all simulators and with all command-line options.