Writing Testbenches using SystemVerilog

The purpose of writing testbenches is to apply stimulus to a design and observe the response. That response must then be compared against the expected behavior.
Generating stimulus is the process of providing input signals to the design under verification as shown in Figure 5-1. From the perspective of the stimulus generator, every input of the design is an output of the generator.
Monitoring is the process of observing output signals from the design under verification as shown in Figure 5-2. From the perspective of the response monitor, every output of the design is an input of the monitor.
| Note | This chapter shows how to apply stimulus and observe response. |
In this chapter, I show how to generate stimulus and observe responses. I also show how to abstract data flowing to and from the design from a physical level composed of l's, O's and elapsed time to a transaction level composed of data objects and procedures. The greatest challenge with stimulus is making sure it is an accurate representation of the environment, not just a simple case. When monitoring responses, one has to be careful not to miss any data and detect as many errors as possible.
| Note | The next chapter shows how to structure a test-bench. |
In the next chapter, I show how to best structure the stimulus generators and response monitors to create a layered self-checking environment. Constrainable random generation is then added on top of the stimulus generators...