TABLE OF CONTENTS A skilled verification engineer must break the "RTL mindset" that most hardware engineers, out of necessity, have grown into. To efficiently accomplish the verification task, you must be well versed in behavioral (i.e., non-synthesizable and highly algorithmic) and transaction-level descriptions. To reliably and correctly use the high-level constructs of SystemVerilog, it is necessary to understand the side effects of the simulation algorithm and the limitations of the language and to understand ways to circumvent those side effects and limitations. This understanding was not required to write RTL models successfully.
This section illustrates the differences between the approaches to writing an RTL model and to writing a high-level model.
| Note | Many guidelines help code RTL models. |
All experienced hardware design engineers are very comfortable with writing synthesizable models. The models conform to a well-defined subset of the System Verilog language and follow one of a few coding styles. Numerous RTL coding guidelines have been published. [1] They help designers obtain efficient implementations: low area, high speed or low power. Guidelines, such as the ones shown in Sample 4-1, can help a novice designer avoid undesirable hardware components, such as latches, internal buses or tristate buffers. More importantly, guidelines such as the ones shown in Sample 4-2, can help maintain identical behavior between the synthesizable model and the gate-level implementation.
To avoid latches, set all outputs of combinatorial blocks to default values at the beginning of the block.
