TABLE OF CONTENTS | Note | C and C++ lack essential concepts for hardware modeling. |
Why hasn't C been used as a hardware description language instead of creating Verilog, VHDL, SystemVerilog and many others? Because the basic C language lacks three fundamental concepts necessary to model hardware designs: connectivity, time and concurrency. Basic C++ also lacks the necessary features to support the verification productivity cycle: randomization, constrainability and functional coverage measurement.
Connectivity is the ability to describe a design using simpler blocks then connecting them together. Schematic capture tools are perfect examples of connectivity support.
Time is the ability to represent how the internal state of a design evolves over time and to control its progression and rate. This concept is different from execution time which is a simple measure of how long a program runs.
Concurrency is the ability to describe actions that occur at the same time, independently of each other.
| Note | C and C++ can be extended. |
Many extensions and coding styles for C or C++ exist that include some or all of these concepts. SystemC is a set of C++ classes to introduce the concept of connectivity, time and concurrency. The SystemC Verification Library is a set of C++ classes that provides support for randomization, constraints and temporal expressions.
The connectivity, time and concurrency concepts are very important to understand when learning to model using a modeling language. Each language implements them in a different fashion, some easier to understand than the...
