TABLE OF CONTENTS | Note | Synthesizable models are limited to bits and vectors. |
The limitation of logic synthesis technology has forced the synthesizable subset into dealing only with data formats that are clearly implementable: bits, vectors of bits and integers. System Verilog adds enums and structs to the synthesizable set, but the various elements of the struct must themselves be bits, bit vectors or integers. High-level models have no such restrictions. You are free to use any data representation that fits your need.
| Note | Work at the same level as the design under verification. |
You must be careful not to let an RTL mindset artificially limit your choice, or to keep you from moving to a higher level of abstraction. You should approach the verification problem at the same level of granularity as the "unit of work" for the design. For an ethernet switch, it is an ethernet MAC frame. For an IP cell router, the unit of work is an entire IP packet. For a SONET framer, the unit of work is a SONET frame. For a video compressor, the unit of work is either a video line or an entire frame, depending on the granularity of the compression. The interesting conditions and testcases are much easier to set up at that level than at the low-level bit interface.
SystemVerilog provides excellent support for abstracting data into high-level representations. This section will only outline how certain data types can be used. You are invited to consult a book...
