TABLE OF CONTENTS | Note | SystemVerilog is object-oriented. |
Object-oriented programming is a methodology that has been used with great success in software engineering for many years. It is the next evolutionary step in language design after structured programming (i.e., the removal of the "go to" statement and introduction of subprograms and control structures). Object-oriented used to be one of those buzzwords used to describe almost everything. In this book, object-oriented is used to identify a methodology that makes use of (and a language that supports) classes, inheritance and polymorphism. SystemVerilog's class data type meets this definition of object-oriented.
| Note | Objects are data and procedures together. |
Classes are a collection of variables and subprograms that create object types. Objects are instances of a class. A class defines an object's state as a collection of data members. A class also defines all possible operations on the object using methods. In SystemVerilog, data members are called class properties while methods are functions and tasks declared within the class. Sample 4-39 shows an example of a class declaration.
| Note | Everything is modeled as an object. |
Physical data types, such as packets, frames and cells, are modeled as objects. Their various fields are data members. Methods exist to calculate and check the value of any CRC or error protection field, translate the field values to and from a sequence of physically transmitted bytes and segment a large object into a series of smaller ones. Processor instructions are modeled as objects. Their...
