TABLE OF CONTENTS | Note | The simulation cycle creates race conditions. |
If you refer to Figure 4-11 and the section titled "Emulating Parallelism on a Sequential Processor" on page 162, you will see that parallel threads are executed one after another, during the same timestep. The order in which the threads are executed is not deterministic. Race conditions exist when multiple concurrent threads compete for the same shared resource over the same time period.
| Note | RTL coding guidelines hide race conditions |
Race conditions are conveniently eliminated when limiting yourself to writing synthesizable code. But once you start using all the features of the language, you may find yourself with code that is not portable across different simulators, different versions of the same simulator or by using different command-line arguments. Any change in the simulation algorithm that causes concurrent threads to be executed in a different order will yield different simulation results.
| Note | Shared variables can create race conditions. |
All variables in SystemVerilog are shared among concurrent threads within their scope (except for automatic variables). Depending on the order in which these concurrent threads read or write these shared variables, different values may be observed.
A read/write race condition happens when two concurrent threads attempt to read and write the same shared variable in the same timestep. If you look at the code in Sample 4-68, you will notice that the first always block assigns the variable count while the second one displays it. But
