TABLE OF CONTENTS Verification is not a testbench, nor is it a series of testbenches. Verification is a process used to demonstrate that the intent of a design is preserved in its implementation. We all perform verification processes throughout our daily lives: balancing a checkbook, tasting a simmering dish, associating landmarks with symbols on a map. These are all verification processes.
In this chapter, I introduce the basic concepts of verification, from its importance and cost, to making sure you are verifying that you are implementing what you want. I present the differences between various verification approaches as well as the difference between testing and verification. I also show how verification is key to design reuse, and I detail the challenges of verification reuse.
The term "testbench" usually refers to simulation code used to create a predetermined input sequence to a design, then optionally to observe the response. Testbenches are implemented using System-Verilog, but they may also include external data files or C routines.
Figure 1-1 shows how a testbench interacts with a design under verification (DUV). The testbench provides inputs to the design and watches any outputs. Notice how this is a completely closed system: no inputs or outputs go in or out. The testbench is effectively a model of the universe as far as the design is concerned. The verification challenge is to determine what input patterns to supply to the design and what is the expected output of a properly working design when...
