TABLE OF CONTENTS As we've seen, the Nested Vectored Interrupt Controller, or NVIC, is an integrated part of the Cortex-M3 processor. It is closely linked to the Cortex-M3 CPU core logic. Its control registers are accessible as memory-mapped devices. Besides control registers and control logic for interrupt processing, the NVIC also contains control registers for the MPU, the SYSTICK Timer, and debugging controls. In this chapter we'll examine the control logic for interrupt processing. MPU and debugging control logic are discussed in later chapters.
The NVIC supports 1 to 240 external interrupt inputs (commonly known as IRQs). The exact number of supported interrupts is determined by the chip manufacturers when they develop their Cortex-M3 chips. In addition, the NVIC also has a Nonmaskable Interrupt (NMI) input. The actual function of the NMI is also decided by the chip manufacturer. In some cases this NMI cannot be controlled from an external source.
The NVIC can be accessed as memory location 0xE000E000. Most of the interrupt control/ status registers are accessible only in privileged mode, except the Software Trigger Interrupt register, which can be set up to be accessible in user mode. The interrupt control/status register can be accessed in word, half word, or byte transfers.
In addition, a few other interrupt-masking registers are also involved in the interrupts. They are the "special registers" covered in Chapter 3 and are accessed via MRS and MSR instructions.
Each external interrupt has several registers associated with it:
Enable and clear enable...
