This chapter focuses on the potential problems that an engineer must recognize when designing an FPGA or CPLD and the design techniques that are used to avoid these problems. More specifically, reading this chapter will help you:

• Learn the fundamental concepts of hardware description languages.

• Appreciate the process of top-down design and how it is used to organize a design and speed up the development time.

• Comprehend how FPGA and CPLD architecture and internal structures affect your design.

• Understand the concept of synchronous design, know how to spot asynchronous circuits, and how to redesign an asynchronous circuit to be synchronous.

• Recognize what problems floating internal nodes can cause and learn how to avoid these problems.

• Understand the consequences of bus contention and techniques for avoiding it.

• Comprehend one-hot state encoding for optimally creating state machines in FPGAs.

• Design testability into a circuit from the beginning and understand various testability structures that are available.