Designing with FPGAs and CPLDs
In this easy to follow guide, the author provides a look at the proprietary designs and methods of CPLDs and FPGAs available to managers, designers and engineers.
TABLE OF CONTENTS Designing with FPGAs and CPLDs
Appendix A: Answer Key
Chapter 1, Prehistory: Programmable Logic to ASICs
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What does the term ASIC mean?
(c) Application Specific Integrated Circuit
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Each programmable device is matched with its description in the following table.
a. PROM (A) A memory device that can be programmed once and read many times.
b. PLA (D) A logic device with a large AND plane and a large OR plane for imple menting different combinations of Boolean logic.
c. PAL (E) A logic device with a large AND plane and a small, fixed number of OR gates for implementing Boolean logic and state machines.
d. CPLD (C) A logic device that is made up of many PAL devices.
e. FPGA (B) A logic device that can be used to design large functions like an ASIC except that it can be programmed quickly and inexpensively.
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Listed is the correct device for each statement PALs or ASICs.
(a) PALs have a short lead-time.
(b) ASICs are high-density devices.
(c) ASICs can implement very complex functions.
(d) PALs do not have NRE charges.
(e) PALs are programmable.
Chapter 2, Complex Programmable Logic Devices (CPLDs)
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What does the term CPLD mean?
(a) Complex Programmable Logic Device
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These are all of the parts of a typical CPLD.
(a) I/O Block
(d) Function Block
(e) Interconnect Matrix
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Which technology is not used for CPLD programmable elements?
(d) DRAM
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Which is not a characteristic of clock drivers
(c) Low power
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The layout of traces that connects a clock driver to the flip-flops in a CPLD...
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