Designing with FPGAs and CPLDs

5.5: Bus Contention

5.5 Bus Contention

Bus contention occurs when two outputs drive the same signal at the same time, as shown in Figure 5.20. This reduces the reliability of the chip because it has multiple drivers fighting each other to drive a common output. If bus contention occurs regularly, even for short times, the possibility of damage to the drivers increases.

One place where this can occur, and that is often ignored, is during the turnaround of a bus. In a synchronous bus, when one device is driving the bus during one clock cycle and a different device is driving during the next clock cycle, there is a short time when both devices may be driving the bus, as shown in Figure 5.19.


Figure 5.19: Contention during synchronous bus turnaround

Figure 5.20: Bus contention the problemNOTE: SEL_A and SEL_B are not mutually exclusive

To avoid contention problems, the designer must ensure that both drivers cannot be asserted simultaneously. This can be accomplished by inserting additional logic, as shown in Figure 5.21. The logic for each buffer enable has been modified so that a buffer is not turned on until its select line is asserted and all other select lines have been de-asserted. Due to routing delays, some contention may still occur, but this circuit has reduced it significantly. Of course, the best solution may be to find better implementations. For example, designers can use muxes instead of tri-state drivers, though muxes are often difficult to implement in FPGAs.

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