Designing with FPGAs and CPLDs
In this easy to follow guide, the author provides a look at the proprietary designs and methods of CPLDs and FPGAs available to managers, designers and engineers.
TABLE OF CONTENTS Designing with FPGAs and CPLDs
Chapter 6: Verification
This chapter deals with verification, a group of methods and techniques used to detect design errors before a chip is created. This chapter describes the activities that are part of the verification process, including how to design testability into a chip and how to fully simulate a chip to ensure that it will function correctly in a completed system. The importance of and effort committed to verification is growing as CPLD and FPGA designs increase in size. In recent projects, I ve found that more manpower is designated for verification than any other phase of the project. Also, all kinds of EDA tools are coming to the market to help with verification. Some of these tools are generic tools, and others are specifically for certain types of chips.
The EDA tools that enable many of the techniques in this chapter are described in detail in Chapter 7.
Objectives
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Understand the use of functional and multilevel simulation for catching design flaws
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Understand the need for regression testing to ensure that changes do not break the design.
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Learn how you can use static timing analysis to very quickly examine a design and determine the maximum frequency and flag all critical paths.Discover uses of assertion languages for simulation and formal verification.132"/>
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Learn where formal verification is appropriate and learn the difference between equivalency checking and functional verification.
6.1 What is Verification?
The term verification is a little nebulous. In the larger domain of IC design, verification generally refers to any technique that is...
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