Designing with FPGAs and CPLDs
In this easy to follow guide, the author provides a look at the proprietary designs and methods of CPLDs and FPGAs available to managers, designers and engineers.
TABLE OF CONTENTS Designing with FPGAs and CPLDs
Glossary
- ABEL
- An early hardware description language used to program PALs.
- antifuse
- Antifuses consist of microscopic structures, which, unlike a regular fuse, normally make no connection. A certain amount of current during programming of the device causes the two sides of the antifuse to connect.
- architecture
- A chip architecture refers to the high level structure of the chip.
- asynchronous
- An asynchronous design is any design that breaks a rule of synchronous design. An asynchronous design has delays that are not strictly controlled by a clock and therefore cannot be easily controlled and predicted.
- ATM
- Asynchronous Transfer Mode. A method of communicating network data at very high speeds.
- BIST
- Built-in self-test. This is a method of including test generation and monitoring circuitry in a chip design so that the chip can perform tests on itself to determine whether it is still working correctly.
- Boolean Algebra
- Invented by nineteenth century mathematician George Boole, this is an algebra that uses only the values 1 and 0. In 1939, Claude Shannon wrote his revolutionary Master s thesis A Symbolic Analysis of Relay and Switching Circuits that described for the first time how Boolean algebra could be applied to the design of computers.
- boundary scan
- Boundary scan uses the scan methodology but scans only nodes around the boundary of the chip, not internal nodes. This is effective for testing the FPGA s connections to the circuit board. It also uses much more refer resources (CLBs and routing) than full scan.
- burn-in test
- A burn-in test is one...
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