Designing with FPGAs and CPLDs
In this easy to follow guide, the author provides a look at the proprietary designs and methods of CPLDs and FPGAs available to managers, designers and engineers.
TABLE OF CONTENTS Designing with FPGAs and CPLDs
Appendix B: Verilog Code for Schematics in Chapter 5
Listing B.1 Figure 5.2
/*********************************************************/// MODULE: asynchronous race condition//// FILE NAME: arace.v// VERSION: 1.0// DATE: June 1, 2002// AUTHOR: Bob Zeidman, Zeidman Consulting// // CODE TYPE: RTL//// DESCRIPTION: This module defines a circuit with an// asynchronous race condition. Note that this circuit// will simulate fine, but a synthesis program won't know// how to synthesize it into a synchronous circuit.///*********************************************************/// DEFINES// TOP MODULEmodule arace( sig1, sig2, out);// PARAMETERS// INPUTSinput sig1; // data inputinput sig2; // clock and clear input// OUTPUTSoutput out; // output// INOUTS// SIGNAL DECLARATIONSwire sig1;wire sig2;reg out;// ASSIGN STATEMENTS// MAIN CODE// Reset conditionalways @(negedge sig2) out <= 0;// Clocked conditionalways @(posedge sig2) out <= sig1;endmodule // arace
Listing B.2 Figure...
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