TABLE OF CONTENTS This chapter is an introduction to the Model Verification Library, also referred to as the Run-Time Model Verification Library. This is the eighth library in the Simulink group of libraries and contains the blocks shown below. The blocks in this library are intended to facilitate creation of self-validating models. We use model verification blocks to check whether the signals exceed specified limits during simulation.
The Check Static Lower Bound block performs a check to verify that each element of the input signal is greater than or equal to a specified lower bound. The block's parameter dialog box allows us to specify the value of the lower bound and whether the lower bound is inclusive. If the verification condition is true, the block takes no action. If not, simulation is halted and an error message is displayed.
In the model of Figure 9.1, the amplitude of a sinusoidal signal may vary 10% from its nominal value of 1 volt. We will configure this model to display error messages when the lower inclusive boundary is specified as -1 volt.
The Signal Generator block is specified for a sine waveform with amplitude 1.1 volt, frequency 0.3 Hz, and the Check Static Lower Bound block is specified at -1 with the Inclusive boundary checked, Enable assertion checked, Output assertion signal checked, and icon type graphic. The Convert block is inserted to...
