20.4.1 Model for a 3-bit Up / Down Counter

A model for the operation of a 3-bit counter with three D Flip Flop blocks, six NAND gate blocks, a NOT gate (Inverter) block, and a Clock block is shown in Figure 20.55. The D Flip Flop and Clock blocks are described in Chapter 19 (Simulink Extras), and the NAND and NOT gates are in the Logic and Bit Operations Library. The D Flip-Flop CLK (clock) inputs are Negative Edge Triggered. The Clock waveform and the D Flip-Flops output waveforms when the Manual Switch block is the Count up position, are shown in Figure 20.56.

Figure 20.55: Model for a 3-bit Up / Down binary counter

Figure 20.56: Waveforms for the model in Figure 20.55

For another example, refer to the Modulo-4 Counter Using Flip Flops Demo model by typing sldemo_flipflops at the MATLAB command prompt.

20.4.2 Model for a 4-bit Ring Counter

The model of Figure 20.57 implements a 4-bit binary counter known as Johnson counter. The D Flip-Flop and Clock blocks are discussed in Chapter 19 (Simulink Extras). The waveforms for this model are shown in Figure 20.58.

Figure 20.57: Model for a 4-bit Johnson counter

Figure 20.58: Waveforms for the model in Figure 20.57

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