2.1 Block Diagram of the Mixed-Signal PLL

As mentioned in Sec. 1.2, the mixed-signal PLL includes circuits that are hybrids of both linear and digital circuits. To see which parts of the system are linear and which are digital, we consider the general block diagram in Fig. 2.1. As shown in Sec. 1.1 every PLL consists of the three blocks: phase detector, loop filter, and voltage-controlled oscillator (VCO). When the PLL is used as a frequency synthesizer, another block is added: a divide-by-N counter. Assuming that the counter divides by a factor N, the frequency of the VCO output signal is forced then to be N times the reference frequency (the frequency of the input signal u ₁). In most cases the divider ratio N is made programmable. We will deal extensively with frequency synthesizers in Chap. 3.

Figure 2.1: Block diagram of the mixed-signal PLL. The symbols defined here are used throughout this chapter. The divide-by- N counter is optional.

When a down-scaler is inserted, the term center frequency becomes ambiguous: the center (radian) frequency ? ₀ can be related to the output of the VCO (as done in Sec. 1.1), but it could also be related to the output of the down-scaler, or in other words, to the input of the PLL. To remove this dilemma, we introduce two different terms for center (radian) frequency: we will use the symbol ? ₀ to denote the center frequency at the...