TABLE OF CONTENTS When analyzing the pull-in range of the PLL (Sec. 2.6.1), we found that a wide pull-in range is most easily achieved by using the PFD as phase detector. Moreover, it showed that the passive lead-lag loop filter performs like a real integrator when driven by the PFD [Eq. (2.100)]. This is because the charge on the loop filter capacitor remains unchanged when the output of the PFD is in the high-impedance state (if we discard leakage currents for the moment). Therefore in most digital PLLs the combination of PFD and passive lead-lag filter is the preferred arrangement (Fig. 2.40a).
As reported by Volgers15 this circuit has a property that can be disturbing in critical applications: the phase detector gain K d of the PFD is not constant as predicted by theory, but varies with the "operating point" of the loop. By "operating point" we mean the average loop filter output signal that is required to create the desired output frequency ? 2 of the VCO.
Let us explain that by a simple consideration. Assume that the PLL is powered from a unipolar supply with U B = 5V, and that the PLL initially operates at its center frequency w 0. Under this condition, the output signal u f of the loop filter will settle at half the supply voltage, i.e., at u f
