TABLE OF CONTENTS This chapter deals with the measurement of PLL parameters. When an ADPLL is used, nothing has to be measured, because all parameters of the circuit are multipliers for clock frequencies and divider ratios of counters. In the case of the DPLL, the parameters are normally well specified in the data sheets. The phase detector gain, for example, depends uniquely on the supply voltage in most cases. For a DPLL built from CMOS technology, the levels of the phase detector output signal come close to the supply rails, so the phase detector gain K d is approximately U B/ ? for the EXOR, U B/2 ? for the JK-flipflop, and U B/4 ? for the PFD. Moreover, the VCO characteristics are well specified on the data sheets of the 4046 and the 7046 ICs (refer to Table 10.1), so there is sufficient information to calculate the values of the external components of the DPLL system. The situation is different in the case of LPLLs, where some parameters are poorly specified for some products.
Many LPLL ICs have a large supply voltage range, and some of the PLL parameters can vary with it. Furthermore, the phase detector gain depends on the level of the reference signal.
It is therefore advantageous if the users are able to measure these parameters themselves. It will be shown in this section that the relevant parameters such as K 0, K d, ? n, ?, and...
