The description of a module in a digital system can be divided into two facets: the external view and the internal view. The external view describes the interface to the module, including the number and types of inputs and outputs. The internal view describes how the module implements its function. In VHDL, we can separate the description of a module into an entity declaration, which describes the external interface, and one or more architecture bodies, which describe alternative internal implementations. These were introduced in Chapter 1 and are discussed in detail in this chapter. We also look at how a design is processed in preparation for simulation or synthesis.

5.1 Entity Declarations

Let us first examine the syntax rules for an entity declaration and then show some examples. We start with a simplified description of entity declarations and move on to a full description later in this chapter. The syntax rules for this simplified form of entity declaration are

entity_declaration <span class="unicode">?</span>      <b class="bold">entity </b>identifier <b class="bold">is</b>          [ <b class="bold">port </b>( <i class="emphasis">port</i>_interface_list ) ; ]          { entity_declarative_item }      <b class="bold">end</b> [ <b class="bold">entity</b> ] [ identifier ] ;interface_list <span class="unicode">?</span>     ( identifier { , <span class="unicode"> </span> } : [ mode ] subtype_indication [ := expression ] ) {; <span class="unicode"> </span> }mode <span class="unicode">?</span> <b class="bold">in</b>